WCH CH32V307V-EVT-R2 
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概述

========

System Block Diagram

.. image:: ../img/CH32V307_arch.jpg


Features

- RISC-V4F processor, max 144MHz system clock frequency;
- Single-cycle multiplication and hardware division, hardware float point unit (FPU) ;
- 64KB SRAM，256KB Flash;
- Supply voltage: 2.5V/3.3V, GPIO unit is supplied independently;
- Multiple low-power modes: sleep/stop/standby;
- Power-on/power-down reset (POR/PDR), programmable voltage detector (PVD);
- 2 general DMA controllers, 18 channels in total;
- 4 amplifiers;
- Single true random number generator (TRNG)
- 2 x 12-bit DAC;
- 2-unit 16-channel 12-bit ADC, 16-channel TouchKey;
- 10 timers;
- USB2.0 full-speed OTG interface;
- USB2.0 high-speed host/device interface (built-in 480Mbps PHY)
- 3 USARTs, 5 UARTs;
- 2 CAN interfaces (2.0B active);
- SDIO interface, FSMC interface, DVP;
- 2 x I2C, 3 x SPI, 2 x IIS;
- 80 I/O ports, can be mapped to 16 external interrupts;
- CRC calculation unit, 96-bit unique chip ID;
- Serial 2-wire debug interface;
- Packages: LQFP64M, LQFP100.


官网链接:'https://www.wch-ic.com/products/productsCenter/mcuInterface?categoryId=70'

参考链接:'https://github.com/openwch/ch32v307'

.. image:: ../img/CH32V307_Core.jpg
.. image:: ../img/CH32V307_Front.jpg
.. image:: ../img/CH32V307_Back.jpg